Static Timing Analysis

Project : TFT
Build Time : 10/07/19 13:10:57
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 97.847 MHz
SPIM_1_IntClock CyMASTER_CLK 6.000 MHz 6.000 MHz 58.907 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 97.847 MHz 10.220 31.447
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P2[1] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 2.032
Route 1 Net_13 MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 4.688
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Skew 0.000
Path Delay Requirement : 166.667ns(6 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 58.907 MHz 16.976 149.691
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_rx_data\/main_3 3.877
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_3 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 4.959
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 61.569 MHz 16.242 150.425
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:load_rx_data\/main_0 3.143
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_0 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 4.959
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 61.584 MHz 16.238 150.429
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_1:BSPIM:count_3\ \SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:load_rx_data\/main_1 3.139
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_1 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 4.959
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 62.205 MHz 16.076 150.591
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:load_rx_data\/main_4 2.977
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_4 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 4.959
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 62.290 MHz 16.054 150.613
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:load_rx_data\/main_2 2.955
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_2 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 4.959
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:TxStsReg\/status_3 65.587 MHz 15.247 151.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_rx_data\/main_3 3.877
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_3 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 5.580
statusicell1 U(0,5) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:TxStsReg\/status_3 68.904 MHz 14.513 152.154
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:load_rx_data\/main_0 3.143
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_0 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 5.580
statusicell1 U(0,5) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:TxStsReg\/status_3 68.923 MHz 14.509 152.158
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_1:BSPIM:count_3\ \SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:load_rx_data\/main_1 3.139
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_1 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 5.580
statusicell1 U(0,5) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:TxStsReg\/status_3 69.701 MHz 14.347 152.320
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:load_rx_data\/main_4 2.977
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_4 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 5.580
statusicell1 U(0,5) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:TxStsReg\/status_3 69.808 MHz 14.325 152.342
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:load_rx_data\/main_2 2.955
macrocell2 U(0,5) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_2 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 5.580
statusicell1 U(0,5) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 6.720
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P2[1] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 2.032
Route 1 Net_13 MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 4.688
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM_1:BSPIM:cnt_enable\/q \SPIM_1:BSPIM:cnt_enable\/main_3 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,5) 1 \SPIM_1:BSPIM:cnt_enable\ \SPIM_1:BSPIM:cnt_enable\/clock_0 \SPIM_1:BSPIM:cnt_enable\/q 1.250
macrocell13 U(1,5) 1 \SPIM_1:BSPIM:cnt_enable\ \SPIM_1:BSPIM:cnt_enable\/q \SPIM_1:BSPIM:cnt_enable\/main_3 2.292
macrocell13 U(1,5) 1 \SPIM_1:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:load_cond\/q \SPIM_1:BSPIM:load_cond\/main_8 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,4) 1 \SPIM_1:BSPIM:load_cond\ \SPIM_1:BSPIM:load_cond\/clock_0 \SPIM_1:BSPIM:load_cond\/q 1.250
macrocell11 U(1,4) 1 \SPIM_1:BSPIM:load_cond\ \SPIM_1:BSPIM:load_cond\/q \SPIM_1:BSPIM:load_cond\/main_8 2.293
macrocell11 U(1,4) 1 \SPIM_1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:cnt_enable\/q \SPIM_1:BSPIM:BitCounter\/enable 3.555
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,5) 1 \SPIM_1:BSPIM:cnt_enable\ \SPIM_1:BSPIM:cnt_enable\/clock_0 \SPIM_1:BSPIM:cnt_enable\/q 1.250
Route 1 \SPIM_1:BSPIM:cnt_enable\ \SPIM_1:BSPIM:cnt_enable\/q \SPIM_1:BSPIM:BitCounter\/enable 2.305
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:ld_ident\/main_5 3.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:ld_ident\/main_5 2.946
macrocell12 U(0,5) 1 \SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:state_2\/main_5 3.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:state_2\/main_5 2.951
macrocell7 U(1,5) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:state_1\/main_5 3.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:state_1\/main_5 2.951
macrocell8 U(1,5) 1 \SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:ld_ident\/main_4 3.605
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM_1:BSPIM:count_3\ \SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:ld_ident\/main_4 2.985
macrocell12 U(0,5) 1 \SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:state_2\/main_3 3.609
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:state_2\/main_3 2.989
macrocell7 U(1,5) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:state_1\/main_3 3.609
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:state_1\/main_3 2.989
macrocell8 U(1,5) 1 \SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:state_2\/main_7 3.715
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:state_2\/main_7 3.095
macrocell7 U(1,5) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ SPIM_1_IntClock
Source Destination Delay (ns)
Net_10/q MOSI(0)_PAD 23.259
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,4) 1 Net_10 Net_10/clock_0 Net_10/q 1.250
Route 1 Net_10 Net_10/q MOSI(0)/pin_input 6.660
iocell1 P2[4] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 15.349
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_11/q SCLK(0)_PAD 22.650
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,4) 1 Net_11 Net_11/clock_0 Net_11/q 1.250
Route 1 Net_11 Net_11/q SCLK(0)/pin_input 5.963
iocell2 P2[3] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 15.437
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
Net_12/q SS(0)_PAD 21.945
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,4) 1 Net_12 Net_12/clock_0 Net_12/q 1.250
Route 1 Net_12 Net_12/q SS(0)/pin_input 5.821
iocell3 P2[7] 1 SS(0) SS(0)/pin_input SS(0)/pad_out 14.874
Route 1 SS(0)_PAD SS(0)/pad_out SS(0)_PAD 0.000
Clock Clock path delay 0.000