Static Timing Analysis

Project : Web Serial API
Build Time : 01/14/25 10:44:02
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock_2 CyMASTER_CLK 10.000 kHz 10.000 kHz 89.095 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:genblk8:stsreg\/status_2 89.095 MHz 11.224 99988.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM:PWMUDB:tc_i\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:status_2\/main_1 2.766
macrocell1 U(0,4) 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/main_1 \PWM:PWMUDB:status_2\/q 3.350
Route 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(0,4) 1 \PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 89.912 MHz 11.122 99988.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.772
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 95.202 MHz 10.504 99989.496
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:status_2\/main_0 3.086
macrocell1 U(0,4) 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/main_0 \PWM:PWMUDB:status_2\/q 3.350
Route 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(0,4) 1 \PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 96.089 MHz 10.407 99989.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.097
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 120.163 MHz 8.322 99991.678
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 2.302
macrocell3 U(0,4) 1 \PWM:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_1 120.163 MHz 8.322 99991.678
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_1 2.302
macrocell4 U(0,4) 1 \PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1526/main_1 120.163 MHz 8.322 99991.678
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1526/main_1 2.302
macrocell5 U(0,4) 1 Net_1526 SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q Net_1526/main_0 129.668 MHz 7.712 99992.288
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q Net_1526/main_0 2.952
macrocell5 U(0,4) 1 Net_1526 SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 141.643 MHz 7.060 99992.940
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,4) 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/clock_0 \PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 2.300
macrocell4 U(0,4) 1 \PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 141.924 MHz 7.046 99992.954
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,4) 1 \PWM:PWMUDB:genblk1:ctrlreg\ \PWM:PWMUDB:genblk1:ctrlreg\/clock \PWM:PWMUDB:genblk1:ctrlreg\/control_7 1.210
Route 1 \PWM:PWMUDB:control_7\ \PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.326
macrocell2 U(0,4) 1 \PWM:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM:PWMUDB:status_0\/q \PWM:PWMUDB:genblk8:stsreg\/status_0 1.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,4) 1 \PWM:PWMUDB:status_0\ \PWM:PWMUDB:status_0\/clock_0 \PWM:PWMUDB:status_0\/q 1.250
Route 1 \PWM:PWMUDB:status_0\ \PWM:PWMUDB:status_0\/q \PWM:PWMUDB:genblk8:stsreg\/status_0 2.325
statusicell1 U(0,4) 1 \PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.686
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,4) 1 \PWM:PWMUDB:genblk1:ctrlreg\ \PWM:PWMUDB:genblk1:ctrlreg\/clock \PWM:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM:PWMUDB:control_7\ \PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.326
macrocell2 U(0,4) 1 \PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 3.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 2.302
macrocell3 U(0,4) 1 \PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_1 3.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_1 2.302
macrocell4 U(0,4) 1 \PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1526/main_1 3.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1526/main_1 2.302
macrocell5 U(0,4) 1 Net_1526 HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,4) 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/clock_0 \PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 2.300
macrocell4 U(0,4) 1 \PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q Net_1526/main_0 4.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q Net_1526/main_0 2.952
macrocell5 U(0,4) 1 Net_1526 HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 4.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.097
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.582
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.810
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.772
datapathcell1 U(0,4) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 8.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:status_2\/main_0 3.086
macrocell1 U(0,4) 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/main_0 \PWM:PWMUDB:status_2\/q 3.350
Route 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(0,4) 1 \PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_2
Source Destination Delay (ns)
Net_1526/q LED1(0)_PAD 22.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 Net_1526 Net_1526/clock_0 Net_1526/q 1.250
Route 1 Net_1526 Net_1526/q LED1(0)/pin_input 5.555
iocell1 P2[1] 1 LED1(0) LED1(0)/pin_input LED1(0)/pad_out 15.891
Route 1 LED1(0)_PAD LED1(0)/pad_out LED1(0)_PAD 0.000
Clock Clock path delay 0.000