Static Timing Analysis

Project : FFT_Example
Build Time : 01/17/25 12:28:07
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 62.814 MHz
UART_1_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 50.689 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 62.814 MHz 15.920 25.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 4.592
macrocell6 U(2,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(2,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 91.199 MHz 10.965 30.702
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.794
macrocell18 U(2,1) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 91.199 MHz 10.965 30.702
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.794
macrocell23 U(2,1) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 91.333 MHz 10.949 30.718
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.778
macrocell24 U(3,1) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 91.341 MHz 10.948 30.719
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.777
macrocell15 U(2,1) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 102.428 MHz 9.763 31.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 4.592
macrocell21 U(2,0) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 102.428 MHz 9.763 31.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 4.592
macrocell22 U(2,0) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 50.689 MHz 19.728 13021.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,1) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 7.456
macrocell5 U(2,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 52.879 MHz 18.911 13022.756
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,1) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 6.639
macrocell5 U(2,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 61.028 MHz 16.386 13025.281
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,1) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 4.114
macrocell5 U(2,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.465 MHz 16.009 13025.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 2.983
macrocell2 U(3,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.236
datapathcell2 U(2,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.531 MHz 15.992 13025.675
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 2.966
macrocell2 U(3,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.236
datapathcell2 U(2,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 63.032 MHz 15.865 13025.802
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 2.839
macrocell2 U(3,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.236
datapathcell2 U(2,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 63.861 MHz 15.659 13026.008
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 3.693
macrocell2 U(3,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.236
datapathcell2 U(2,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 64.429 MHz 15.521 13026.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 3.249
macrocell5 U(2,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 65.764 MHz 15.206 13026.461
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_3 5.516
macrocell3 U(3,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_3 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.260
statusicell1 U(3,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_load_fifo\/main_3 69.798 MHz 14.327 13027.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,1) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_load_fifo\/main_3 9.567
macrocell16 U(2,1) 1 \UART_1:BUART:rx_load_fifo\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 4.592
macrocell21 U(2,0) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 4.592
macrocell22 U(2,0) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.438
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.777
macrocell15 U(2,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.439
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.778
macrocell24 U(3,1) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 7.455
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.794
macrocell18 U(2,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 7.455
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.794
macrocell23 U(2,1) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 12.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.661
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 4.592
macrocell6 U(2,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(2,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,1) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.867
statusicell2 U(2,0) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.873
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.683
macrocell12 U(2,0) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.879
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.689
macrocell9 U(3,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.879
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.689
macrocell10 U(3,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.783
macrocell16 U(2,1) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_2\/main_5 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_2\/main_5 2.783
macrocell18 U(2,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_0\/main_5 3.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_0\/main_5 2.795
macrocell15 U(2,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_3\/main_5 3.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_3\/main_5 2.795
macrocell17 U(2,1) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 3.419
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 2.799
macrocell15 U(2,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 3.419
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 2.799
macrocell17 U(2,1) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 28.130
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 2.669
macrocell1 U(3,0) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx_1(0)/pin_input 6.241
iocell2 P3[0] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 14.620
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000