Static Timing Analysis

Project : M95P32
Build Time : 07/15/24 10:20:57
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
SPIM_1_IntClock CyMASTER_CLK 200.000 kHz 200.000 kHz 72.140 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 5000ns(200 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 72.140 MHz 13.862 4986.138
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_rx_data\/main_3 3.112
macrocell1 U(0,4) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_3 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.610
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 73.768 MHz 13.556 4986.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_1:BSPIM:count_3\ \SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:load_rx_data\/main_1 2.806
macrocell1 U(0,4) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_1 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.610
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 73.784 MHz 13.553 4986.447
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:load_rx_data\/main_0 2.803
macrocell1 U(0,4) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_0 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.610
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 73.817 MHz 13.547 4986.453
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:load_rx_data\/main_2 2.797
macrocell1 U(0,4) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_2 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.610
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM_1:BSPIM:RxStsReg\/status_6 74.705 MHz 13.386 4986.614
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ \SPIM_1:BSPIM:sR8:Dp:u0\/clock \SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.580
Route 1 \SPIM_1:BSPIM:rx_status_4\ \SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM_1:BSPIM:rx_status_6\/main_5 3.621
macrocell4 U(0,3) 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/main_5 \SPIM_1:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/q \SPIM_1:BSPIM:RxStsReg\/status_6 2.335
statusicell2 U(0,3) 1 \SPIM_1:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 74.761 MHz 13.376 4986.624
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:load_rx_data\/main_4 2.626
macrocell1 U(0,4) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_4 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.610
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:TxStsReg\/status_3 81.440 MHz 12.279 4987.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_rx_data\/main_3 3.112
macrocell1 U(0,4) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_3 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.377
statusicell1 U(1,3) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:RxStsReg\/status_6 83.229 MHz 12.015 4987.985
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:rx_status_6\/main_3 3.890
macrocell4 U(0,3) 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/main_3 \SPIM_1:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/q \SPIM_1:BSPIM:RxStsReg\/status_6 2.335
statusicell2 U(0,3) 1 \SPIM_1:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:TxStsReg\/status_3 83.521 MHz 11.973 4988.027
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_1:BSPIM:count_3\ \SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:load_rx_data\/main_1 2.806
macrocell1 U(0,4) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_1 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.377
statusicell1 U(1,3) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:TxStsReg\/status_3 83.542 MHz 11.970 4988.030
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:load_rx_data\/main_0 2.803
macrocell1 U(0,4) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_0 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.377
statusicell1 U(1,3) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:state_2\/main_7 3.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:state_2\/main_7 2.616
macrocell6 U(0,4) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:state_1\/main_7 3.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:state_1\/main_7 2.616
macrocell7 U(0,4) 1 \SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:ld_ident\/main_7 3.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:ld_ident\/main_7 2.616
macrocell11 U(0,4) 1 \SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 Net_1/main_9 3.246
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 Net_1/main_9 2.626
macrocell5 U(0,4) 1 Net_1 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:state_2\/main_5 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:state_2\/main_5 2.789
macrocell6 U(0,4) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:state_1\/main_5 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:state_1\/main_5 2.789
macrocell7 U(0,4) 1 \SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:ld_ident\/main_5 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:ld_ident\/main_5 2.789
macrocell11 U(0,4) 1 \SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 Net_1/main_7 3.417
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 Net_1/main_7 2.797
macrocell5 U(0,4) 1 Net_1 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:state_2\/main_3 3.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:state_2\/main_3 2.800
macrocell6 U(0,4) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:state_1\/main_3 3.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:state_1\/main_3 2.800
macrocell7 U(0,4) 1 \SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_1_IntClock
Source Destination Delay (ns)
MISO(0)_PAD \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 17.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO(0)_PAD MISO(0)_PAD MISO(0)/pad_in 0.000
iocell1 P6[0] 1 MISO(0) MISO(0)/pad_in MISO(0)/fb 7.816
Route 1 Net_4 MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 6.025
datapathcell1 U(0,4) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ SPIM_1_IntClock
Source Destination Delay (ns)
Net_2/q SCLK(0)_PAD 24.970
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,3) 1 Net_2 Net_2/clock_0 Net_2/q 1.250
Route 1 Net_2 Net_2/q SCLK(0)/pin_input 7.682
iocell3 P12[5] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 16.038
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1/q MOSI(0)_PAD 23.462
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,4) 1 Net_1 Net_1/clock_0 Net_1/q 1.250
Route 1 Net_1 Net_1/q MOSI(0)/pin_input 5.992
iocell2 P12[6] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 16.220
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000