Static Timing Analysis

Project : Web Serial API
Build Time : 07/30/24 09:36:33
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 56.619 MHz
UART_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 50.005 MHz
Clock_2 CyMASTER_CLK 10.000 kHz 10.000 kHz 90.351 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:genblk8:stsreg\/status_2 90.351 MHz 11.068 99988.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM:PWMUDB:tc_i\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:status_2\/main_1 2.613
macrocell9 U(3,3) 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/main_1 \PWM:PWMUDB:status_2\/q 3.350
Route 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 2.315
statusicell3 U(3,3) 1 \PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 91.333 MHz 10.949 99989.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.599
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 97.135 MHz 10.295 99989.705
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:status_2\/main_0 2.880
macrocell9 U(3,3) 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/main_0 \PWM:PWMUDB:status_2\/q 3.350
Route 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 2.315
statusicell3 U(3,3) 1 \PWM:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 98.030 MHz 10.201 99989.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.891
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 120.077 MHz 8.328 99991.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 2.308
macrocell27 U(3,3) 1 \PWM:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_1 120.077 MHz 8.328 99991.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_1 2.308
macrocell28 U(3,3) 1 \PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1526/main_1 120.077 MHz 8.328 99991.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1526/main_1 2.308
macrocell29 U(3,3) 1 Net_1526 SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q Net_1526/main_0 130.787 MHz 7.646 99992.354
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q Net_1526/main_0 2.886
macrocell29 U(3,3) 1 Net_1526 SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 141.743 MHz 7.055 99992.945
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,3) 1 \PWM:PWMUDB:genblk1:ctrlreg\ \PWM:PWMUDB:genblk1:ctrlreg\/clock \PWM:PWMUDB:genblk1:ctrlreg\/control_7 1.210
Route 1 \PWM:PWMUDB:control_7\ \PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.335
macrocell26 U(3,3) 1 \PWM:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 141.844 MHz 7.050 99992.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,3) 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/clock_0 \PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 2.290
macrocell28 U(3,3) 1 \PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 56.619 MHz 17.662 24.005
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 6.364
macrocell6 U(2,3) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.290
datapathcell3 U(2,3) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 82.823 MHz 12.074 29.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 6.376
macrocell22 U(2,5) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 82.905 MHz 12.062 29.605
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 6.364
macrocell23 U(2,3) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 88.339 MHz 11.320 30.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 5.622
macrocell19 U(2,4) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 88.339 MHz 11.320 30.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.622
macrocell24 U(2,4) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 88.441 MHz 11.307 30.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.609
macrocell16 U(2,4) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 89.550 MHz 11.167 30.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.469
macrocell25 U(3,4) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 50.005 MHz 19.998 13021.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,5) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 6.308
macrocell2 U(2,5) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.900
datapathcell2 U(2,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 56.513 MHz 17.695 13023.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 5.065
macrocell2 U(2,5) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.900
datapathcell2 U(2,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.501 MHz 17.391 13024.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,5) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.701
macrocell2 U(2,5) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.900
datapathcell2 U(2,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 59.235 MHz 16.882 13024.785
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 4.609
macrocell5 U(2,4) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.313
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.287 MHz 16.867 13024.800
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,5) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 3.177
macrocell2 U(2,5) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.900
datapathcell2 U(2,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 62.794 MHz 15.925 13025.742
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,4) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 3.652
macrocell5 U(2,4) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.313
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 64.998 MHz 15.385 13026.282
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 3.112
macrocell5 U(2,4) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.313
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 67.186 MHz 14.884 13026.783
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,4) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 2.611
macrocell5 U(2,4) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.313
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:TxSts\/status_0 67.326 MHz 14.853 13026.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,5) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:tx_status_0\/main_1 7.438
macrocell3 U(2,5) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_1 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.315
statusicell1 U(2,5) 1 \UART:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 68.985 MHz 14.496 13027.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 4.136
macrocell6 U(2,3) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.290
datapathcell3 U(2,3) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM:PWMUDB:status_0\/q \PWM:PWMUDB:genblk8:stsreg\/status_0 1.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,3) 1 \PWM:PWMUDB:status_0\ \PWM:PWMUDB:status_0\/clock_0 \PWM:PWMUDB:status_0\/q 1.250
Route 1 \PWM:PWMUDB:status_0\ \PWM:PWMUDB:status_0\/q \PWM:PWMUDB:genblk8:stsreg\/status_0 2.324
statusicell3 U(3,3) 1 \PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.695
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,3) 1 \PWM:PWMUDB:genblk1:ctrlreg\ \PWM:PWMUDB:genblk1:ctrlreg\/clock \PWM:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM:PWMUDB:control_7\ \PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.335
macrocell26 U(3,3) 1 \PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 3.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:prevCompare1\/main_0 2.308
macrocell27 U(3,3) 1 \PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_1 3.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM:PWMUDB:status_0\/main_1 2.308
macrocell28 U(3,3) 1 \PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1526/main_1 3.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM:PWMUDB:cmp1_less\ \PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1526/main_1 2.308
macrocell29 U(3,3) 1 Net_1526 HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,3) 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/clock_0 \PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 2.290
macrocell28 U(3,3) 1 \PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q Net_1526/main_0 4.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q Net_1526/main_0 2.886
macrocell29 U(3,3) 1 Net_1526 HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 4.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.891
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/clock \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.810
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ \PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.599
datapathcell4 U(3,3) 1 \PWM:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 7.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,3) 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/clock_0 \PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM:PWMUDB:runmode_enable\ \PWM:PWMUDB:runmode_enable\/q \PWM:PWMUDB:status_2\/main_0 2.880
macrocell9 U(3,3) 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/main_0 \PWM:PWMUDB:status_2\/q 3.350
Route 1 \PWM:PWMUDB:status_2\ \PWM:PWMUDB:status_2\/q \PWM:PWMUDB:genblk8:stsreg\/status_2 2.315
statusicell3 U(3,3) 1 \PWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 7.657
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.469
macrocell25 U(3,4) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 7.797
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.609
macrocell16 U(2,4) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 7.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 5.622
macrocell19 U(2,4) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 7.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.622
macrocell24 U(2,4) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 8.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 6.364
macrocell23 U(2,3) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 8.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 6.376
macrocell22 U(2,5) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 14.192
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_208 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 6.364
macrocell6 U(2,3) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.290
datapathcell3 U(2,3) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(2,4) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.325
statusicell2 U(3,4) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 3.407
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 2.787
macrocell17 U(2,4) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_6 3.407
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_6 2.787
macrocell19 U(2,4) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_load_fifo\/main_7 3.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_load_fifo\/main_7 2.800
macrocell17 U(2,4) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_2\/main_7 3.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_2\/main_7 2.800
macrocell19 U(2,4) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_0\/main_7 3.423
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_0\/main_7 2.803
macrocell16 U(2,4) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_3\/main_7 3.423
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_3\/main_7 2.803
macrocell18 U(2,4) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_6 3.429
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_6 2.809
macrocell16 U(2,4) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_3\/main_6 3.429
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_3\/main_6 2.809
macrocell18 U(2,4) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_1\/main_0 3.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_1\/main_0 2.881
macrocell22 U(2,5) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_2
Source Destination Delay (ns)
Net_1526/q LED(0)_PAD 24.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(3,3) 1 Net_1526 Net_1526/clock_0 Net_1526/q 1.250
Route 1 Net_1526 Net_1526/q LED(0)/pin_input 8.152
iocell8 P6[3] 1 LED(0) LED(0)/pin_input LED(0)/pad_out 15.011
Route 1 LED(0)_PAD LED(0)/pad_out LED(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 28.825
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,5) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_203/main_0 3.212
macrocell1 U(3,4) 1 Net_203 Net_203/main_0 Net_203/q 3.350
Route 1 Net_203 Net_203/q Tx_1(0)/pin_input 5.452
iocell10 P0[6] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.561
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000